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74ALVCH16245 Low-Voltage 16-Bit Transceiver with Bus Hold 1.8/2.5/3.3 V
(3-State, Non-Inverting)
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The 74ALVCH16245 is an advanced performance, non-inverting 16-bit transceiver. It is designed for very high-speed, very low-power operation in 1.8 V, 2.5 V or 3.3 V systems. The 74ALVCH16245 is designed with byte control. It can be operated as two separate octals, or with the controls tied together, as a 16-bit wide function. The Transmit/Receive (T/Rn) inputs determine the direction of data flow through the bi-directional transceiver. Transmit (active-HIGH) enables data from A ports to B ports; Receive (active-LOW) enables data from B to A ports. The Output Enable inputs (OEn), when HIGH, disable both A and B ports by placing them in a HIGH Z condition. The data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic state.
MARKING DIAGRAM
48
48
74ALVCH16245DT
1
AWLYYWW
TSSOP-48 DT SUFFIX CASE 1201 A WL YY WW
1 = Assembly Location = Wafer Lot = Year = Work Week
* Designed for Low Voltage Operation: VCC = 1.65 - 3.6 V * 3.6 V Tolerant Inputs and Outputs * High Speed Operation: 3.0 ns max for 3.0 to 3.6 V * * * * * * * *
3.7 ns max for 2.3 to 2.7 V 6.0 ns max for 1.65 to 1.95 V Static Drive: 24 mA Drive at 3.0 V 12 mA Drive at 2.3 V 4 mA Drive at 1.65 V Supports Live Insertion and Withdrawal Includes Active Bushold to Hold Unused or Floating Inputs at a Valid Logic State IOFF Specification Guarantees High Impedance When VCC = 0 V Near Zero Static Supply Current in All Three Logic States (40 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 250 mA @ 125C ESD Performance: Human Body Model >2000V; Machine Model >200V Second Source to Industry Standard 74ALVCH16245
ORDERING INFORMATION
Device 74ALVCH16245DTR Package TSSOP Shipping 2500/Tape & Reel
To ensure the outputs activate in the 3-state condition, the output enable pins should be connected to VCC through a pull-up resistor. The value of the resistor is determined by the current sinking capability of the output connected to the OE pin.
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 1
Publication Order Number: 74ALVCH16245/D
74ALVCH16245
T/R1 1 B0 2 B1 3 GND 4 B2 5 B3 6 VCC 7 B4 8 B5 9 GND 10 B6 11 B7 12 B8 13 B9 14 GND 15 B10 16 B11 17 VCC 18 B12 19 B13 20 GND 21 B14 22 B15 23 T/R2 24 48 OE1 47 A0 46 A1 45 GND 44 A2 43 A3 42 VCC 41 A4 40 A5 39 GND 38 A6 37 A7 36 A8 35 A9 34 GND 33 A10 32 A11 31 VCC 30 A12 29 A13 28 GND 27 A14 26 A15 25 OE2 T/R1 48 OE1 25 OE2 24 T/R2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 1 1 1
T/R1
1 48
T/R2
24 25
OE1
OE2
A0:7
B0:7
A8:15
B8:15
One of Eight
Figure 2. Logic Diagram
EN1 EN2 EN3 EN4
1
1
2 3 5 6 8 9 11
2
3
12 13 14 16
Figure 1. 48-Lead Pinout (Top View) PIN NAMES
Pins OEn T/Rn A0-A15 B0-B15 Function Output Enable Inputs Transmit/Receive Inputs Side A Inputs or 3-State Outputs Side B Inputs or 3-State Outputs
4
17 19 20 22 23
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
Figure 3. IEC Logic Diagram
Inputs OE1 L L H T/R1 L H X Outputs O tp ts Bus B0:7 Data to Bus A0:7 Bus A0:7 Data to Bus B0:7 High Z State on A0:7, B0:7 OE2 L L H
Inputs T/R2 L H X Outputs O tp ts Bus B8:15 Data to Bus A8:15 Bus A8:15 Data to Bus B8:15 High Z State on A8:15, B8:15
H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable
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74ALVCH16245
MAXIMUM RATINGS (Note 1)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 2) Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 30 to 35 Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Above VCC and Below GND at 125C (Note 6) VI < GND VO < GND Parameter Value *0.5 to )4.6 *0.5 to )4.6 *0.5 to )4.6 *50 *50 $50 $100 $100 *65 to )150 260 )150 90 Level 1 UL 94 V-O @ 0.125 in u2000 u200 N/A $250 V Unit V V V mA mA mA mA mA C C C C/W
ILATCH-UP
Latch-Up Performance
mA
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. IO absolute maximum rating must be observed. 2. Measured with minimum pad spacing on an FR4 board, using 10 mm-by-1 inch, 2-ounce copper trace with no air flow. 3. Tested to EIA/JESD22-A114-A. 4. Tested to EIA/JESD22-A115-A. 5. Tested to JESD22-C101-A. 6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO TA Dt/DV Supply Voltage Input Voltage Output Voltage Operating Free-Air Temperature Input Transition Rise or Fall Rate VCC = 2.5 V $ 0.2 V VCC = 3.0 V $ 0.3 V Parameter Operating Data Retention Only (Note 7) (Active State) (3-State) Min 2.3 1.5 -0.5 0 0 *40 0 0 Max 3.6 3.6 3.6 VCC 3.6 )85 20 10 Unit V V V C ns/V
7. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
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74ALVCH16245
DC ELECTRICAL CHARACTERISTICS
TA = *405C to )855C Symbol VIH Parameter HIGH Level Input Voltage (Note 8) 1.65 V v VCC t 2.3 V 2.3 V v VCC v 2.7 V 2.7 V t VCC v 3.6 V VIL LOW Level Input Voltage (Note 8) 1.65 V v VCC t 2.3 V 2.3 V v VCC v 2.7 V 2.7 V t VCC v 3.6 V VOH HIGH Level Output Voltage 1.65 V v VCC v 3.6 V; IOH = *100 mA VCC = 1.65 V; IOH = *4 mA VCC = 2.3 V; IOH = *6 mA VCC = 2.3 V; IOH = *12 mA VCC = 2.7 V; IOH = *12 mA VCC = 3.0 V; IOH = *12 mA VCC = 3.0 V; IOH = *24 mA VOL LOW Level Output Voltage 1.65 V v VCC v 3.6 V; IOL = 100 mA VCC = 1.65 V; IOL = 4 mA VCC = 2.3 V; IOL = 6 mA VCC = 2.3 V; IOL = 12 mA VCC = 2.7 V; IOL = 12 mA VCC = 3.0 V; IOL = 24 mA II II(HOLD) ( ) Input Leakage Current Minimum Bus-hold Input Current 1.65 V v VCC v 3.6 V; 0 V v VI v 3.6 V VCC = 3.6 V; VIN = 0 to 3.6 V VCC = 3.0 V, VIN = 0.8 V VCC = 3.0 V, VIN = 2.0 V VCC = 2.3 V, VIN = 0.7 V VCC = 2.3 V, VIN = 1.7 V VCC = 1.65 V, VIN = 0.58 V VCC = 1.65 V, VIN = 1.07 V IOZ IOFF ICC 3-State Output Current Power-Off Leakage Current Quiescent Supply Current (Note 9) Increase in ICC per Input 1.65 V v VCC v 3.6 V; 0 V v VO v 3.6 V; VI = VIH or VIL VCC = 0 V; VI or VO = 3.6 V 1.65 V v VCC v 3.6 V; VI = GND or VCC 1.65 V v VCC v 3.6 V; 3.6 V v VI, VO v 3.6 V 2.7 V t VCC 3.6 V; VIH = VCC * 0.6 V 75 *75 45 *45 25 *25 $10 10 40 $40 750 mA mA mA mA VCC * 0.2 1.2 2.0 1.7 2.2 2.4 2.0 0.2 0.45 0.4 0.7 0.4 0.55 $5.0 $500 mA mA V Condition 0.65 1.7 2.0 0.35 0.7 0.8 V VCC V Min VCC Max Unit V
DICC
8. These values of VI are used to test DC electrical characteristics only. 9. Outputs disabled or 3-state only.
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74ALVCH16245
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits TA = -40C to +85C VCC = 3.0 V to 3.6 V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Input to Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output-to-Output Skew (Note 11) Waveform 1 2 2 Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.0 3.0 4.4 4.4 4.1 4.1 0.5 0.5 VCC = 2.3 V to 2.7 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.7 3.7 5.7 5.7 5.2 5.2 0.5 0.5 VCC = 1.65 V to1.95 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 6.0 6.0 9.3 9.3 7.6 7.6 0.75 0.75 Unit ns ns ns ns
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification. 11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Condition Note 12 Note 12 Note 12, 10MHz Typical 6 7 20 Unit pF pF pF
12. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC. VIH An, Bn Vm tPLH Bn, An Vm WAVEFORM 1 - PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VIH OEn, T/Rn tPZH An, Bn tPZL An, Bn Vm Vm Vm tPHZ Vm 0V VOH Vy 0V tPLZ VCC Vx VOL Vm tPHL Vm VOL 0V VOH
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
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74ALVCH16245
VCC Symbol VIH Vm Vx Vy 3.3 V 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V VCC RL CL RL 6 V or VCC x 2 OPEN GND 2.5 V 0.2 V VCC VCC/2 VOL + 0.15 V VOH - 0.15 V 1.8 V 0.15 V VCC VCC/2 VOL + 0.15 V VOH - 0.15 V
PULSE GENERATOR RT
DUT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6 V at VCC = 3.3 0.3 V; VCCx 2 at VCC = 2.5 0.2 V; 1.8 V 0.15 V GND
CL = 50 pF for VCC = 3.0 0.3 V RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W)
Figure 5. Test Circuit
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74ALVCH16245
10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2 mm (0.008") E A0 B1 K0 SEE NOTE 2 SEE NOTE 2 F
K t D TOP COVER TAPE P2
P0
W
+
B0 P
+
+
D1 FOR COMPONENTS 2.0 mm x 1.2 mm AND LARGER
FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0
EMBOSSMENT USER DIRECTION OF FEED
CENTER LINES OF CAVITY
*TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX R MIN TAPE AND COMPONENTS SHALL PASS AROUND RADIUS R" WITHOUT DAMAGE
BENDING RADIUS
EMBOSSED CARRIER
EMBOSSMENT
10
MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE
100 mm (3.937")
1 mm MAX
TAPE 1 mm (0.039") MAX 250 mm (9.843")
TYPICAL COMPONENT CENTER LINE
CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 6. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 13 and 14)
Tape Size 24mm B1 Max 20.1mm (0.791") D D1 E F K P P0 P2 R T W
1.5 + 0.1mm 1.5mm 1.75 11.5 11.9 mm 16.0 4.0 2.0 30 mm 0.6 mm 24.3 mm -0.0 Min 0.1 mm 0.10 mm Max 0.1 mm 0.1 mm 0.1 mm (1.18") (0.024") (0.957") (0.059 (0.060") (0.069 (0.453 (0.468") (0.63 (0.157 (0.079 +0.004" -0.0) 0.004") 0.004") 0.004") 0.004") 0.004") 13. Metric Dimensions Govern-English are in parentheses for reference only. 14. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity.
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74ALVCH16245
t MAX
1.5 mm MIN (0.06") A 20.2 mm MIN (0.795")
13.0 mm 0.2 mm (0.512" 0.008")
50 mm MIN (1.969")
FULL RADIUS
G
Figure 7. Reel Dimensions
REEL DIMENSIONS
Tape Size 24 mm A Max 360 mm (14.173") G 24.4 mm + 2.0 mm, -0.0 (0.961" + 0.078", -0.00) t Max 30.4 mm (1.197")
DIRECTION OF FEED
BARCODE LABEL POCKET HOLE
Figure 8. Reel Winding Direction
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74ALVCH16245
CAVITY TAPE
TOP TAPE
TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN
COMPONENTS
TAPE LEADER NO COMPONENTS 400 mm MIN
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
User Direction of Feed
Figure 10. Reel Configuration
F
L
48 Leads
Figure 11. Package Footprint
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EEEEEEE E EEEEEEEEEE EEEE EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E
G
EEEEEEEE E EEEEEEEEE EE EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E
K
74ALVCH16245
PACKAGE DIMENSIONS
TSSOP DT SUFFIX CASE 1201-01 ISSUE A
48X
K REF 0.12 (0.005)
M
J J1
48 25
0.254 (0.010)
L
B -U- N
1 24
PIN 1 IDENT.
A -V-
N F DETAIL E M 0.25 (0.010)
D 0.076 (0.003) -T- SEATING
PLANE
C DETAIL E G H
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EEE CCC EEE CCC EEE CCC
TU
S
V
S
K K1
M
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 --1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 --0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 --0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 --0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_
TU
S
-W-
74ALVCH16245
Notes
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74ALVCH16245
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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74ALVCH16245/D

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